In the past, an individual integrated circuit (“IC”) would be manufactured for a circuit that performs a specific function. Such circuits are sometimes referred to as “modules.” For example, a module may be a radio frequency (“RF”) circuit, such as a low-noise amplifier or power amplifier, an analog circuit, such as a filter, a mixed-signal circuit, such as an analog-to-digital converter (“ADC”) or a digital-to-analog converter (“DAC”), or a digital circuit, such as a microprocessor, as well as circuits that perform other functions. Various different types of test processes have been developed for testing ICs that contain a single module.
Traditionally, RF, analog, and mixed-signal circuits are tested by applying a test stimulus and verifying that the functional specifications for the circuit are satisfied. Functional specifications are parameters such as common-mode rejection ratio, power supply rejection ratio, signal-to-noise ratio, integral nonlinearity, differential nonlinearity, and other similar metrics. This method is referred to as “specification testing.” The traditional specification testing is time consuming and faster methods have been sought. Two such faster test methods are described below.
U.S. patent application Ser. No. 09/837,887, now pending, to Voorakaranam, et al., entitled Method and Apparatus for Low Cost Signature Testing of Analog and RF Circuits, incorporated herein in its entirety by reference, discloses a method for testing analog circuits. In the Voorakaranam method, a sample of ICs is tested using the traditional specification testing method. In addition, IC specification and design information are used to derive test stimuli that will produce a set of synthesized measurements. The sample ICs are retested using the derived test stimuli. The measurements obtained from the retesting are related to the IC specifications through nonlinear regression mapping resulting in a set of synthesized test measurements. A pass/fail decision i.e., whether the tested IC is “good” or “bad,” is made on the basis of the synthesized test measurements. An advantage of this method is that direct measurements of the IC specifications is not required. Because the synthesized test measurements are mapped into the IC specifications using nonlinear regression mapping, the synthesized test measurements implicitly contain the IC specifications. U.S. patent application Ser. No. 09/838,359 now U.S. Pat. No. 6,476,741, to Cherubal, et al., entitled Method and System for Making Optimal Estimates of Linearity Metrics of Analog-to-Digital Converters, incorporated herein in its entirety by reference, discloses a method for testing analog-to-digital converter circuits. The Voorakaranam and Cherubal methods are referred to herein as the “implicit specification testing” or “signature testing” method.
With the ability to manufacture ICs that have many more transistors than was possible in the past, it is now possible to manufacture an SOC on a single IC and also to manufacture a system-on-a-package (“SOP”). An SOP refers to two of more ICs that have been bonded together in a single package. For the purposes of this disclosure, the term “system-on-a-package-or-a-chip” (“SOPC”) will be used herein to refer to both SOC and SOP. Typically, an SOPC includes a number of modules (“embedded modules”). Use of the traditional specification testing method to test an SOPC is even more time consuming than with an IC having a single module. Further, it may not be possible to test an SOPC using specification based testing methods. For these reasons, it would be desirable to employ the implicit specification testing methods to test modules of an SOPC.